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CPU Cache Coherency: MESI Protocol

[ Main Memory ]

+-------------+

| Data_A: 0x01|

+-------------+

+----------+ +----------+

| Core 1 | | Core 2 |

| L1 Cache| | L1 Cache|

+----------+ +----------+

| Data_A: 0x01 | E |

+------------+ +------------+

Bus Transaction: Read Data_A

Core 2 loads Data_A, Core 1's state changes to Shared.

+----------+ +----------+

| Core 1 | | Core 2 |

+------------+ +------------+

| Data_A: 0x01 | S | | Data_A: 0x01 | S |

+------------+ +------------+

Core 1 modifies Data_A. Core 2's copy becomes Invalid.

Bus Transaction: Invalidate!

+----------+ +----------+

| Core 1 | | Core 2 |

+------------+ +------------+

| Data_A: 0x02 | M | | Data_A: 0x01 | I |

+------------+ +------------+

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